The present invention relates in general to a technique for use in controlling a bus of a data processor having a multi-bus configuration in which plural bases are connected by a bus bridge circuit; and, more particularly, the invention relates, for example, to a technique that is effective when applied to a microcomputer in which a processor core and an image processing module are connected to different buses.
Japanese Unexamined Patent Publication No. 2003-85127 (Patent Document 1) discloses a dual bus system in which peripheral bridges are provided, so that a bus master connected to a low-speed bus and a bus master connected to a high-speed bus can simultaneously occupy the buses. An external memory is connected to a first bus via an external bus controller, another memory is connected to a second bus via an external memory controller, and a bus master of the first bus can access the other memory via an external memory controller on the second bus side.